The present invention relates, generally, to apparatus and methods of phase detection, and, in particular embodiments to methods and apparatus for high speed phase detection and clock regeneration in which variable circuit delays are inserted into phase detector circuitry and controlled by feedback loops in order to adjust signal propagation times.
As the demand for data bandwidth increases, so does the demand for high bandwidth optical data transmission techniques.
Typically, there are two basic ways that digital data is formatted in fiber optic systems. The two formats are the return-to-zero (RZ) format and the non-return-to-zero (NRZ) format. In the NRZ format, each bit of data occupies a separate timeslot and is either a binary 1 or a binary 0 during that time period. In contrast, in the RZ format, a time period is allowed for each bit. Each bit is transmitted as a pulse or an absence of a pulse. Both formats are referenced to a system clock. The system clock, however, is not a separate signal and must be recovered from the data. A clock signal may be recorded, for instance from NRZ data, by using the transition occurrences within the data transmitted. The process of recovering a clock signal from transmittal data is typically referred to as clock data recovery (CDR). Clock data recovery subsystems are a key block for digital communications and telecommunication circuits. CDR systems are also used in a variety of other digital systems, for example disk drives.
Commonly clock data recovery circuits are based on the use of phase lock loops (PLL). Unlike phase lock loops that are used in wireless applications, a CDR PLL operates on random data, such as but not limited to non-return-to-zero data, instead of a sine wave or modulated sine wave signal. With NRZ data, the clock signal, which is encoded with the data, must be regenerated from the data since the data must eventually be processed synchronously. A further complication with clock and data recovery circuits is that the data spectrum is broadband. This is in contrast to the narrow band spectrum PLLs, which are commonly encountered in typical PLL applications such as synthesizers, demodulators, and modulators.
In CDR circuits, a regenerated clock signal is typically used to retime the data through a Flip-Flop, which is used as a decision circuit. This retiming of data comprises the data recovery function of the CDR circuit. By retiming the data, the data stream is essentially recreated and time domain jitter, which may be present in the NRZ signal or produced by the NRZ receiver circuitry, may be greatly reduced.
A typical application using clock and data recovery circuits is a SONET (synchronous optical network) system. In SONET systems, the CDR subsystem has difficult performance specifications to meet in terms of jitter tolerance, jitter generation, jitter transfer, bit error rate, and phase margin. These performance specifications are held within tight tolerances so that SONET systems may deliver high quality data with a low BER (bit error rate).
A key parameter affecting the quality of data received is the phase margin. Phase margin is the phase relationship between data and clock that results in correct data being reproduced. In other words, if the phase margin of a decision circuit that is decoding the transmitted data needed is exceeded, the probability that errors can result may increase. In 1% order to minimum phase margin error, the clock should cause the data to be sampled at times when the data is stable, that is, at a time when the data is not in transition. Such sampling requires that the sampling edge of the clock signal reside at or near the middle of the transmitted data bit. This condition, in which the clock resides in the middle of the data bit, is referred to as centered clock/data. To achieve the condition of centered clock/data the phase lock loop within the clock and data recovery circuit must maintain a particular static phase offset between the clock and data. This static phase offset requirement is typically more stringent than the lock requirement in standard PLL applications. In addition, because the clock regeneration is using a data stream to regenerate the clock, the performance of the phase detector will be dependent on the data patterns within the data transmitted.
Commonly Hogge type phase detectors are used in clock data recovery circuits. Process, temperature, voltage, data pattern, transition density, and matching circuit delay variations affect the performance of Hogge type phase detectors. Such variations, which are difficult to compensate, result in a combination of increased static phase error, reduced phase margin, and high pattern dependant jitter. In high-speed designs, the effect of such variations is exacerbated. Accordingly, design issues become more critical for proper circuit operation as data rate increases.
Accordingly, to overcome limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading the present specification, preferred embodiments of the present invention relate to apparatus and method for assuring proper phase margin, in order to achieve high rates of reliable data reproduction.
A preferred embodiment of the present system comprises the integration of Hogge and Alexander type phase detectors.
In particular, preferred embodiments of the present system provide a linear type phase detector, exemplary a Hogge type phase detector. The linear phase detector has matching delays inserted within the circuitry within the data and/or clock paths to compensate for mismatch in the different propagation speeds of data and clock signals through the circuitry.
Signal propagation through circuitry changes with a variety of variables such as the process used to fabricate the circuit, actual fabrication parameters, temperature, voltage, input signal level and even the data pattern received. Because a variety of variables affect propagation delays, it is very difficult to match propagation delays statically through clock and data circuits. It is important to match clock and data propagation times through circuitry because the maximum data frequency can be achieved if the transition times for the data and clock are matched. In order to match the propagation delays of the data and clock signals through circuitry variable circuit delays are placed in the clock and/or data path. The phase mismatch between the data and clock is measured locally using a digital phase detector also known as a xe2x80x9cbang-bangxe2x80x9d phase detector. Once the phase difference between the clock and data is determined, a delay upstream of the clock and/or data signal can be controlled in order to match propagation delays and hence the phase of the data and clock signals.
Because the factors affecting propagation delay within a circuit change slowly, the control loops used to control the propagation delays within the circuitry must be low bandwidth. Additionally the control loop bandwidth should be low so that control loops for the inserted circuit delays not react to transitory upsets in data or clock signals. The local matching control loop should be significantly slower than the overall phase detector loop. In practice, slowing the local control loop is problematical. The traditional method of slowing the response of a control loop, such as an AFC loop, is to add an integrator with a large time constant. Such large time constants are traditionally accomplished by inserting a RC (Resistor-Capacitor) network with a large time constant. Such a large time constant can be fabricated by adding external resistors or capacitors to the phase detector circuitry, which is contained in an integrated circuit. Adding such external components not only adds to the cost of the circuitry, but also consumes precious input/output pins upon the integrated circuit containing the loop.
In one embodiment of the present invention, a method, which may accomplish the same purpose as the large time constant RC network and yet be entirely fabricated efficiently on an integrated circuit, is used to produce the low frequency control circuitry for the delays. In this embodiment, the high speed up and down outputs of a bang-bang type phase detector, such as an Alexander phase detector, are coupled into opposite sides of a chip capacitor. The capacitor integrates the high frequency pulses from the bang-bang phase detector such that the analog voltage across the capacitor is proportional to the average difference in the number of up and down pulses produced by the bang-bang phase detector. If the voltage across the capacitor is zero volts, then an equal number of up and down pulses have been produced. A zero voltage across the capacitor means that the clock and data are essentially in proper phase. If a greater number, on average, of up pulses then down pulses have been produced, voltage across the capacitor will be positive. If, however, on the average, a greater number of down pulses than up pulses have been produced, the voltage across the capacitor will be negative. A positive voltage across the capacitor indicates that the phase of the data is leaving the clock. A negative voltage across the capacitor indicates that the data is lagging the clock. The voltage across the capacitor is then coupled into a comparator or a one-bit digital-to-analog converter. The one-bit digital-to-analog converter will have an output of zero if the voltage across the capacitor is positive and will have an output of one if the voltage across the capacitor is negative. The output of the digital-to-analog converter is then coupled into an up/down counter. An up/down counter is coupled to a clock signal and if the output of the digital-to-analog converter is zero volts, the counter will count up. If the output of the digital-to-analog converter is one volt, the up/down counter will count down. The output of the up/down counter can then be decimated in a variety of ways. The up/down counter may couple into a divide-by circuit, it may be sampled at long intervals or the least significant bits can be merely dropped. The decimated output of the counter can then be used to control the circuit delay thereby closing the control loop.
The response of the control loop can be controlled by several different factors. First, by slowing the clock of the up/down counter, the rate of counting can be slowed. Second, by dividing the output of the up/down counter the response of the loop can also be controlled. Because the response time of the loop controlling the local circuit delays is easily controlled, the loops can be adjusted for varying circuit conditions. For example, a faster loop can be used on startup to speed lock acquisition. Inversely, the loop can be slowed in very noisy environments in order to prevent it from reacting to noise.
Further embodiments of the invention may employ multiple variations in order to achieve different results. For example, multiple loops can be employed to match clock and data phases at various points within the circuitry. Matching individual delays, instead of matching an overall delay may achieve a finer control of the data and clock phases within the circuitry, thereby allowing the maximum speed at which the circuitry can operate to increase.
In other embodiments, other aspects of the present invention can be utilized. For example, the counter coupled to the output of the one-bit digital-to-analog converter can be preloaded to a default value upon startup of the circuitry. Such a value can be predetermined and recorded within the integrated circuit or the value maybe obtained by recording the value of the counter during a steady state operating condition. Then on startup the steady state values may be loaded into the counter thereby providing a close approximation to the ideal value. Such preloading on startup can speed the acquisition of lock of the overall system. The counter value may also be recorded and averaged so that upon loss of signal the loop can be restarted with a value close to the previous steady state value.
Other embodiments of the present invention can be used to tailor the response speed of delay elements to the transition density of incoming data. Phase detectors, such as Hogge phase detectors, have a phase detector gain that is proportional to the transition density of the incoming data. For example, the overall gain of a Hogge phase detector detecting a 11001100 pattern is generally only half as fast as the same Hogge phase detector detecting a 10101010 pattern. The individual phase delays within the circuitry should be controlled with a frequency response that is lower than the bandwidth of the overall data loop. By observing the transition density of the data, and hence the gain of the primary loop, the frequency response of the delay control loops can be made to be less than that of the primary loop. The frequency response of the delay control loop(s) may be controlled dynamically, to be less than the frequency response of the overall phase detector loop, even as the response of the overall control loop is changing due to changes within incoming data pattern.